Imperas updates free reference model riscvOVPsimPlus

Imperas Software announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension and architectural validation test suites.

The P (or Packed SIMD/DSP) extension is a significant addition to the flexibility of the modular RISC-V ISA (Instruction Set Architecture); it supports real-time data processing applications as part of the main processor pipeline without the need for the associated inefficiencies of a co-processor. For processor hardware verification, a basic test suite helps ensure implementations have a basic software level compatibility to the new P extension as a reference to the developers’ interpretation of the written specification.

riscvOVPsimPlus is a popular free ISS (Instruction Set Simulator) that is an envelope model that can be configured to cover all of the ratified RISC-V specifications and standard extensions. Also included are several Architectural Validation Test Suites, which form a basic test plan for software level compatibility within the specification definitions. The Imperas models are available as open-source and licensed under the Apache 2.0 flexible open-source license.

The Imperas RISC-V architectural validation test suites are collections of tests focused on specific ISA extensions that provide basic testing of instruction execution and usage of the full range of operands with a set of representative data values.

Contenuti correlati

• 
  Dolphin Design selects Imperas for processor functional design verification

  Imperas Software announced that ImperasDV has been adopted by Dolphin Design for RISC-V processor verification for the Panther DSP/AI Accelerator IP from Dolphin Design. The open standard ISA (Instruction Set Architecture) of RISC-V offers processor developers many...
• 
  Imperas collaborates with MIPS and Ashling to accelerate RISC-V application software development

  Imperas Software announced with MIPS and Ashling a new 3-way collaboration to support developers across all aspects of RISC-V software development for advanced processor applications. Based on the Imperas reference models for the MIPS eVocore P8700 RISC-V...
• 
  Imperas releases free ISS for RISCV-V CORE-V developers in the OpenHW ecosystem

  Imperas Software made available the first release of riscvOVPsimCOREV as free ISS (Instruction Set Simulator) based on the Imperas reference models of the OpenHW Groups processor RISC-V core IP. riscvOVPsimCOREV can be configured for the complete range...