Mentor’s Calibre and Analog FastSPICE platforms achieve certification for TSMC’s newest processes

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Mentor, a Siemens business, announced that it has achieved certification for a broad array of Mentor integrated circuit (IC) design tools for TSMC’s N5 and N6 process technologies.

TSMC’s N5 and N6 process technologies help many IC design companies boost performance, shrink form factors and reduce power consumption for processors targeting highly competitive markets such as the automotive, Internet of Things, high performance computing, 5G mobile/infrastructure, artificial intelligence and other spaces.

“Mentor’s long and fruitful partnership with TSMC continues to help our joint customers deliver highly innovative and differentiated ICs,” said Joe Sawicki, executive vice president for Mentor’s IC Segment. “Mentor is pleased to extend this partnership with recent certifications of Mentor design platforms for TSMC’s newest and most advanced semiconductor process technologies.”

Among the many Mentor IC design technologies recently certified for TSMC’s N5 and N6 processes are the Calibre nmPlatform, which is the IC physical verification industry leader, the Calibre xACT extraction tool – a component of the larger Calibre nmPlatform that delivers robust parasitic extraction functionality and highly accurate parasitic data for post-layout analysis and simulation and the Mentor’s Analog FastSPICE (AFS) Platform, which provides leading-edge circuit verification for nanometer analog, radio frequency (RF), mixed-signal, memory and custom digital circuits.

In addition to these certifications, Mentor also announced that its AFS platform now supports TSMC’s mobile and high performance computing (HPC) design platform. The certification enables Mentor’s customers targeting analog, mixed-signal and radio frequency (RF) designs for HPC applications to verify their chips with confidence in the latest TSMC processes.

Mentor also announced a collaboration with TSMC to further leverage Calibre’s 3DSTACK packaging tools to support TSMC’s CoWoS packaging technology that features a silicon interposer as a solution for inter-die port connectivity checks and Calibre xACT for parasitic extraction.

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