Renesas Electronics Corporation announced the development of two technologies that reduce the energy and voltage application time for the write operation of spin-transfer torque magnetic random-access memory (STT-MRAM, hereinafter MRAM). On a 20-megabit (Mbit) test chip with embedded MRAM memory cell array in a 16 nm FinFET logic process, a 72 percent reduction in write energy and a 50 percent reduction in the voltage application time were confirmed. The new technologies are a self-termination write scheme with slope pulse application, in which the write pulse is automatically and adaptively terminated due to write characteristics of each memory cell; and a write sequence to optimize the number of bits, to which write voltage is applied simultaneously. Combined, these technologies make it possible to reduce the power consumption and increase the speed of write operations.
Renesas continues to develop incremental technologies aimed at the application of embedded MRAM technology in MCU products. Moving forward, Renesas will endeavor to further increase capacity, speed, and power efficiency to accommodate a range of new applications.