Imperas Software made available the first release of riscvOVPsimCOREV as free ISS (Instruction Set Simulator) based on the Imperas reference models of the OpenHW Groups processor RISC-V core IP.
riscvOVPsimCOREV can be configured for the complete range of the OpenHW CORE-V processor IP portfolio, including the RTL-frozen CV32E40P (formally known as PULP RI5CY), the under-development CV32E40S and CV32E40X, plus the upcoming CVA6-32/64 bit (formally known as PULP ARIANE), and will be extended overtime to cover the future roadmap of CORE-V.
An ISS is a software based representation of a processor that can be used to test and develop software on a standard host x86 PC machine. The main advantages of an ISS over a traditional hardware development platform are the ease-of-use features that help the programmer with debug, control and visibility of code running in simulation.
To support integration with IDE’s and other software design methodologies such as CI/CD (Continuous Integration and Continuous Deployment) platforms, riscvOVPsimCOREV features configuration and interface options such as debug port and trace to allow easy integration.
riscvOVPsimCOREV is licensed as closed source freeware.