7 fellows & 7 thoughts about Moore’s Law – “We must teach chips to feel pain”

Pubblicato il 19 novembre 2015

When I was a doctorate student in the 1980s there was lots of wild speculation about Moore’s Law: give it another 10 years and transistors will stop getting smaller, they were saying back then. But in the end, the creativity of engineers turned out to be greater than the pessimism of the forecasters.

Yet today I believe that we are close to the end of Moore’s Law. Increasingly fewer companies are now manufacturing chips, because it is becoming too expensive and too complex. It is a race of elimination that will gradually see Moore’s Law extinguished. And, of course, we are also virtually at the limits of the physical boundaries involved. Transistors today are just a few dozen atoms in length. And you can’t make things smaller than one atom.

In actual fact, Moore’s Law ceased some time ago to be driven purely by making the dimensions of transistors smaller. More and more, gains in performance are coming from the introduction of new materials (first for interconnects and gate dielectrics, and now also for the transistor channel itself). This is done by replacing planar by 3D MOSFET transistor architectures, while in the future we will even see MOSFETs being replaced by alternative concepts such as tunnelFETs, carbon nanotubes or spin wave devices.

However, this last technology will have enormous implications for chip designers. When that happens, the whole ecosystem built around the MOSFET, with models, simulation tools, libraries, etc. will have to be replaced or adapted significantly.  The question is whether the investment, effort and risk involved with upsetting this whole ecosystem may outweigh the benefits of such a switch.

In the area of the reliability of chips, there are enormous challenges ahead if we abandon the tried-and-tested MOSFET transistor. First and foremost, if we introduce new materials and designs for our devices, we will have to embark on a learning curve in which we will need to understand any new failure mechanisms that come along. For the classic MOSFET, that means a learning curve of 50 years.

But if we introduce new concepts, we will have to start virtually back at zero again. Also in the future we will probably not be able to guarantee that all of a chip’s transistors will continue to operate reliably throughout the whole proposed service life. Unless we approach the whole thing differently, that is. Design, device and technology engineers will have to work much more intensively together to ensure a reliable system, even if it is built using transistors that are not 100% reliable.

Research into this is already underway at imec. If we use innovative design methodologies that detect and resolve problems during runtime, a reliable system can be achieved. This can be compared with the human body feeling pain when something is wrong. So we need to teach transistors to feel ‘pain’ so that we can adjust the parameters at runtime and make the system continue to keep working that way. This means that innovation will no longer mainly come from the technology, but from smart design and carefully considered applications. It promises to be a major challenge!

About the author

Guido Groeseneken received the M.Sc. degree in electrical and mechanical engineering (1980) and the Ph.D degree in applied sciences (1986), both from the KU Leuven, Belgium.  In 1987 he joined the R&D Laboratory of IMEC (Interuniversity Microelectronics Center) in Leuven, Belgium, where he is acting as scientific fellow, covering research fields of advanced devices and reliability physics of Sub 22nm CMOS technologies. Since 2014 he is also responsible for the academic relations of imec with universities worldwide. Until 2014 he was managing the device reliability group. From October 2005 until April 2007 he was responsible for the IMEC Post CMOS Nanotechnology program within IMEC’s core partner research program.  Since 2001 he is Professor at the KU Leuven, where he is managing a European Erasmus Mundus Master program in Nanoscience and nanotechnology.  Since January 2005 he is elected to the grade of IEEE Fellow

He has made contributions to the fields of non-volatile semiconductor memory devices and technology, reliability physics of VLSI-technology, hot carrier effects in MOSFET’s, time-dependent dielectric breakdown of oxides, Negative-Bias-Temperature Instability effects, ESD-protection and –testing, plasma processing induced damage, electrical characterization of semiconductors and characterization and reliability of high k dielectrics. Recently he has also interest in nanotechnology for post-CMOS applications, such as carbon nanotubes for interconnect and sensor applications, tunnel FET’s for alternative ultra-low power devices etc.

He has served as a technical program committee member of several international scientific conferences, among which the IEEE International Electron Device Meeting (IEDM), the European Solid State Device Research Conference (ESSDERC), the International Reliability Physics Symposium (IRPS), the IEEE Semiconductor Interface Specialists Conference (SISC) and the EOS/ESD Symposium. From 2000 until 2002 he also acted as European Arrangements Chair of IEDM. In 2005 he was the General Chair of the Insulating Films on Semiconductor (INFOS) conference, organized in Leuven, Belgium and in 2008 he co-organized the European ESREF conference in Maastricht, The Netherlands. Finally from 1999 until 2006 he acted as an editor of IEEE Transactions on Electron Devices. Since 2006 he is member of the IEEE EDS Fellow evaluation commission. Since 2012 he is member of the IEEE J.J. Ebers award committee.

Guido Groeseneken, imec fellow and fellow IEEE Electron Devices Society

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