7 fellows & 7 thoughts about Moore’s Law – “Moore’s Law will continue for a long time yet, but we will have to scale in a more ‘specialized’ way”
Moore’s Law is not a law of dimensions, but of economics. The law states that electronic systems will become increasingly smaller and increasingly cheaper and/or acquire more functions. The best example of this is our smartphone. In the first place, we can make systems smaller and smaller, because researchers continue to be successful in making the ultimate building block – the transistor – smaller. But you certainly shouldn’t overlook the importance of 3D integration. Concepts such as system-in-package (SiP) and system-on-chip (SoC) also make it possible to make systems more compact, without making any new technological progress in reducing the size of the elementary building blocks themselves.
In particular 3D-SoC will become very important if Moore’s Law – i.e. the miniaturization of systems – is to be able to keep on going for much longer. At the moment, 2D-SoC is used mainly. A chip is made up of various little islands, each with a specific function: a microprocessor, a memory function, an analog function, a crossbar interconnect, etc. It involves a monolithic integration of all of the parts, with all ‘islands’ produced in the same technology. If in this case, the most advanced technology is used, a SoC approach can become very expensive. Just think about using EUV lithography, which you would only want to use for chip islands that actually would benefit from this advanced technology.
To resolve this problem, there will be a shift from 2D-SoC to 3D-SoC. This latter concept allows each functional island on the chip to be produced using the most suitable (and best cost) technology. For example, for the memory function we use the most advanced technology. But this is not required for the sensor function and so we use ‘older’ technology. All of the chip components can then be stacked on one another in three dimensions. Which means you don’t have to make any compromises (which is sometimes the case with 2D-SoC). This solution makes the system cheaper, more performant and also more compact thanks to the 3D stacking.
The biggest challenge currently for 3D SoC is to make this concept economically achievable. In particular the testing of each layer of the chip has to be well developed.
For this reason, I believe that Moore’s Law will continue to apply for a long time yet, but we will have to miniaturize things in a more ‘specialized’ way. The smallest technologies will be used very specifically for the functions that benefit from it. So, it is no longer a matter of ‘one size fits all’.
About the author
Eric Beyne is program director of 3D system integration at imec. This team performs R&D in the field of high-density interconnection and packaging techniques focused on “system-in-a-package” integration, 3D-interconnections, wafer-level packaging, RF front-end design and technology using integrated passives and RF-MEMS as well as research on packaging reliability including thermal and thermo-mechanical characterization. Eric Beyne obtained a degree in electrical engineering in 1983 and the PhD in Applied Sciences in 1990, both from the University of Leuven (KU Leuven). He has been with imec since 1986. He is president of the IMAPS-Benelux committee, member of the IMAPS-Europe Liaison committee, elected member of the board of governors of the IEEE-CPMT society and IEEE-CPMT Strategic Director for Region 8.
Eric Beyne, program director of 3D system integration, imec
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